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Physical Verification
Fully Qualified Runsets
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Fully Qualified Runsets
Foundry
Process Node
Runset Type
Available from Foundry
TSMC
65/55
DRC
Yes
TSMC
65/55
Fill
Yes
TSMC
65
LVS
Yes
TSMC
55
LVS
Yes
TSMC
45LP/40G
DRC
Yes
TSMC
45LP/40G
Fill
Yes
TSMC
45LP/40G
PAD DRC
Yes
TSMC
45LP
LVS
Yes
TSMC
40LP
LVS
Yes
TSMC
40G
LVS
Yes
TSMC
28LP
DRC
Yes
TSMC
28LP
Fill
Yes
TSMC
28LP
LVS
Yes
TSMC
28HP
DRC
Yes
TSMC
28HP
Fill
Yes
TSMC
28HP
LVS
Yes
Common Platform
65 G
DRC
Yes
Common Platform
65 G
LVS
Q4 2010
GLOBALFOUNDRIES
65 LPe
DRC
Yes
GLOBALFOUNDRIES
65 LPe
LVS
Q4 2010
Common Platform
45 G/LP
DRC
Yes - Samsung
Samsung
45 G/LP
DRC addendum
Yes - Samsung
Common Platform
32 LP
DRC
Q4 2010
Samsung
32 LP
DRC addendum
Q4 2010
Common Platform
28 LP
DRC
Yes
Common Platform
28 LP
LVS
Q3 2010
Common Platform
28 G/HP
DRC
Yes
GLOBALFOUNDRIES
28 HPM
DRC
Q3 2010
Common Platform
28 G/HP
LVS
Q3 2010
Common Platform
28
Fill
Q4 2010
IBM
12S
DRC
Yes
IBM
13S
DRC
Yes
IBM
12S
Methodology
Yes
Physical Verification News
Adapteva uses Magma’s RTL-to-GDSII Flow to Tape Out a 28-nm 64-Core Microprocessor Chip
eSilicon Tapes Out 28-nm 1.5GHz Microprocessor Cluster for Embedded Platforms with Talus and Quartz
Magma Congratulates Winners of the MUSIC India 2011 “Best Paper” Awards
Quartz DRC Qualified to Support GLOBALFOUNDRIES’ DRC+ Flow for 28 nm and Below
Physical Verification Articles
GSA Forum:
Seizing the Emerging Silicon Opportunities Created by Vertical Integration
EE Times:
Building 3D-ICs – Tool Flow and Design Software
SemiWiki:
Magma eSilicon-one Keynote
Learn More
Webinar:
Silicon One SoC Sign-off Solution -- Tekton, QCP and Quartz DRC
Video:
Silicon One Initiative Launched at DAC
Webcast:
Get a Clear Vision of 20-nm Design Success
White Paper:
Talus qDRC - Moving Sign-Off into the Implementation Flow
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